1. Field of the Invention
The present invention relates to a pulse output circuit, a shift register and a display device. Note that in this specification, display devices include a liquid crystal display device using a liquid crystal display element as a pixel, and a self-luminous display device using a self-luminous element, e.g., an electroluminecent (EL) element. Driver circuits for a display device are circuits which perform processing for displaying an image by inputting image signals to pixels arranged in the display device, and which include pulse output circuits, e.g., a shift register and an inverter, and amplifier circuits.
2. Description of the Related Art
In recent years, display devices having a semiconductor thin film formed on an insulating substrate such as a glass substrate, particularly active matrix display devices using thin film transistors (TFTs) have become widely available and have been used in various products. An active matrix display device using TFTs has several hundred thousand to several million pixels arranged in a matrix form and displays an image by controlling charge on each of the pixels by means of a TFT provided in the pixel.
Techniques relating to polysilicon TFTs have recently been developed which comprise forming driver circuits on a substrate on the periphery of a pixel portion by using TFTs simultaneously with the formation of pixel TFTs constituting pixels. Such techniques have contributed to the development of display devices reduced in size and in power consumption. Also, such display devices have become indispensable to display units for mobile information terminals which have found application in an increasing number of application areas in recent years.
Ordinarily, a complementary metal-oxide-semiconductor (CMOS) circuit using a combination of an n-channel TFT and a p-channel TFT is used as a circuit constituting driver circuits for display devices. A shift register will be described as an example of this CMOS circuit with reference to FIGS. 11A, 11B, and 11C. A section in a frame 1100 indicated by a dotted line is a circuit forming one stage for outputting a pulse. Only three of the pulse output stages of the shift register are shown in FIG. 11A. Each circuit forming one stage is constituted by clocked inverters 1101 and 1103, and an inverter 1102. FIG. 11B shows details of the circuit configuration. Referring to FIG. 11B, TFTs 1104 to 1107 constitute a clocked inverter 1101, TFTs 1108 and 1109 constitute a clocked inverter 1102, and TFTs 1110 to 1113 constitute a clocked inverter 1103.
Each of the TFTs constituting the circuit has three electrodes: a gate electrode, a source electrode, and a drain electrode. However, the source region and the drain region cannot be discriminated from each other because of a structural characteristic of the TFT. In ordinary CMOS circuits, one of the source and drain regions of the n-channel TFT at a lower potential is used as a source electrode, while the other at a higher potential is used as a drain electrode. Also, one of the source and drain regions of the p-channel TFT at a higher potential is used as a source electrode, while the other at a lower potential is used as a drain electrode. In the description of the connection of TFTs in this specification, the source and drain electrodes are referred to as a first electrode and a second electrode, respectively, or as a second electrode and a first electrode, respectively, to avoid confusing them one with the other.
The operation of the circuit will be described. In the following description of the operation of TFTs, a conducting state when a channel is formed between impurity regions by application of a potential to the gate electrode is represented by “ON”, and a non-conducting state when the impurity region channel is not formed is represented by “OFF”.
Referring to FIGS. 11A and 11B and FIG. 11C, which is a timing chart, a clock signal (hereinafter referred to as “CK”) and an inverted clock signal (hereinafter referred to as “CKB”) are respectively input to the TFTs 1107 and 1104. A start pulse (hereinafter referred to as “SP”) is input to the TFTs 1105 and 1106. When CK is high level; CKB is low level; and SP is high level, each of the TFTs 1106 and 1107 is ON and low level is output to be input to the inverter 1102 constituted by the TFTs 1108 and 1109. The inverter 1102 inverts the input low level and outputs high level through an output node (SRout 1). Thereafter, CK becomes low level and CKB becomes high level, while SP is high level. Then, a holding operation by means of a loop formed by the inverter 1102 and the clocked inverter 1103 is performed. Outputting high level through the output node is thus continued. CK and CKB then become high level and low level, respectively, and the clocked inverter 1101 again performs the write operation. Low level is thus output through the output node since SP has already become low level. Subsequently, when CK and CKB become low level and high level, respectively, the holding operation is again performed. Low level output from the output node at this time is held in the loop formed by the inverter 1102 and the clocked inverter 1103.
The operation of one stage is thus performed. In the next stage, the connections with respect to CK and CKB are reversed and the same operation as described above is performed according to the reversed polarity of the clock signal. The same operation is repeated according to the polarity of the clock signal alternately changed. Sampling pulses are thus output successively, as shown in FIG. 11C.
A feature of the CMOS circuit should be mentioned which resides in limiting power consumed by the entire circuit. That is, a current flows only at a moment when a change in logic state (from high level to low level or from low level to high level) occurs and no current flows when a logic state is maintained (although in actuality a small leak current flows).
The demand for display devices using liquid crystals or self-luminous elements is growing rapidly with the development of mobile electronic devices reduced in size and weight. However, it is difficult to effectively reduce the manufacturing cost of such display devices by improving the yield, etc. It is naturally conceivable that the demand will further grow rapidly. Therefore, it is desirable to supply display devices at a reduced cost.
A method of forming an active layer pattern, a wiring pattern, etc., by performing exposure and etching using a plurality of photomasks is ordinarily used as a method of fabricating a driver circuit on an insulator. Since the number of manufacturing steps is a dominant factor in determining the manufacturing cost, a manufacturing method using a reduced number of manufacturing steps is ideal for manufacture of driver circuits. If driver circuits can be formed by using TFTs of only one of two conductivity types, i.e., the n-channel or p-channel type, instead of being formed of CMOS circuits, part of the ion doping process can be removed and the number of photomasks can be reduced.
FIG. 9A illustrates a CMOS inverter (I) ordinarily used, and inverters (II) and (III) formed by using only TFTs of one polarity or by using only one TFT. The inverter (II) has a TFT used as a load. The inverter (III) has a resistor used as a load. The operation of each inverter will be described.
FIG. 9B shows the waveform of a signal input to each inverter. The input signal amplitude is low level/high level=VSS/VDD (VSS<VDD). It is assumed that VSS=0 V.
The operation of the circuit will be described. To describe the operation simply and explicitly, it is assumed here that the threshold voltages of n-channel TFTs are equal to each other and are represented by V thN across the board, and that, similarly, the threshold voltage of a p-channel TFT is represented by a constant value V thP.
When a signal such as shown in FIG. 9B is input to the CMOS inverter, and when the potential of the input signal is high level, the p-channel TFT 901 is OFF and the N-channel TFT 902 is ON. The resulting potential at the output node is low level. Conversely, when the potential of the input signal is low level, the p-channel TFT 901 is ON and the N-channel TFT 902 is OFF. The resulting potential at the output node is high level (FIG. 9C).
The operation of the inverter (II) using a TFT as a load will next be described with respect to a case where a signal such as shown in FIG. 9B is input. When the input signal is low level, the n-channel TFT 904 is OFF. The load TFT 903 is operating in a saturated state. As a result, the potential at the output node is pulled up toward a high level. On the other hand, when the input signal is high level, the n-channel TFT 904 is ON. The potential at the output node is pulled down toward a low level if the current capacity of the n-channel TFT 904 is sufficiently larger than the current capacity of the load TFT 903.
In the inverter (III) using a resistor as a load, the ON resistance of the n-channel TFT 906 is set to a value sufficiently smaller than the resistance value of a load resistor 905. In this inverter, therefore, when the input signal is high level, the n-channel TFT 906 is ON and the potential at the output node is pulled down toward a low level. When the input signal is low level, the n-channel TFT 906 is OFF and the potential at the output node is pulled down toward a high level.
However, there is a problem described below with each of the inverter using a TFT as a load and the inverter using a resistor as a load. FIG. 9D shows the waveform of the output from the inverter using the TFT 903 as a load. When the output is high level, the potential of the output is lower than VDD by an amount indicated by 907. If in the load TFT 903 the terminal on the output node side is a source while the terminal on the power supply VDD side is a drain, the potential at the gate electrode is VDD, since the gate electrode and the drain region are connected to each other. The condition for maintaining the load TFT in the ON state is (TFT 903 gate-source voltage>V thN). Therefore the highest level to which the potential at the output node can be increased is (VDD−V thN). That is, the amount 907 is equal to V thN. Further, when the output is low level, the potential of the output is higher than VSS by an amount indicated by 908, depending on the ratio of the current capacities of the load TFT 903 and the n-channel TFT 904. To bring the output potential sufficiently close to VSS, it is necessary to sufficiently increase the current capacity of the n-channel TFT 904 relative to that of the load TFT 903. Similarly, referring to FIG. 9E showing the waveform of the output from the inverter using the resistor 905 as a load, the potential of the output is higher by an amount indicated by 909, depending on the ratio of the resistance value of the load resistor 905 and the ON resistance of the n-channel TFT 906. That is, in use of the above-described inverter formed by using only one TFT or only TFTs of one polarity, the amplitude of the output signal is attenuated relative to the amplitude of the input signal.